SYSGO at RISC-V Summit Europe 2025: Driving Innovation in Safety and AI

SYSGO is proud to participate in the RISC-V Summit Europe 2025 from 12-15 May, the premier event for industry and research communities advancing the open RISC-V architecture in Europe. As an active contributor to the RISC-V ecosystem, SYSGO is involved in several key European research initiatives, including TRISTAN, ISOLDE, and REBECCA—all partially funded through European programs, and all reflecting our commitment to innovation and collaboration.

At the summit, SYSGO joins forces with the Technical University of Crete, Exascale Performance Systems, and Klepsydra Technologies AG to present a paper on "The REBECCA Hardware/Software Edge AI Platform". This cutting-edge platform is built around the CVA6 processor, utilizing a chiplet-based design and shared memory architecture to deliver highly efficient real-time AI processing. With HyperRAM for fast data access and a custom software stack designed to maximize performance and security—including a hypervisor layer and AI acceleration capabilities—REBECCA stands at the forefront of Edge AI innovation.

Download the Paper (0.4 MB, PDF)

Beyond REBECCA, SYSGO remains actively engaged in broader RISC-V developments. We recently attended a face-to-face meeting of the RISC-V Safety Working Group, reinforcing our dedication to safe and secure RISC-V solutions. Our PikeOS real-time operating system and hypervisor, along with our ELinOS Embedded Linux, are fully available for RISC-V platforms, offering developers robust tools for building reliable embedded systems.

A major milestone in our ongoing RISC-V work came on April 25, 2025, when our contribution to the Trace Ingress Port (TIP)—part of the TRISTAN project—was officially accepted into the CVA6 repository (https://github.com/openhwgroup/cva6/commit/f314dcb136ed373db8332e30a897fa06db4aae43). Developed in collaboration with the University of Bologna and Thales Research & Technology, TIP adds powerful real-time tracing capabilities to CVA6. This feature enables developers to capture instruction-level execution data without interrupting the program flow which offers an essential tool for debugging rare bugs, optimizing code, and conducting advanced profiling and performance analysis. With standardized encoding and live streaming support, TIP brings a new level of visibility and control to RISC-V development.

SYSGO is excited to contribute to the growing momentum of the RISC-V ecosystem in Europe and beyond. Whether in safety-critical environments or at the AI edge, we're committed to pushing the boundaries of what's possible with open hardware and trusted software.